From powering watches to phones, handheld consoles to desktop PCs, office servers to data centers, processors can be found everywhere and in every size possible. That last aspect is set to take a gargantuan leap forward thanks to the world’s top chip manufacturer and its next generation of system-on-wafer packing.
As reported by PC Watch, TSMC has recently announced that it has commenced development of a new version of its SoW (System-on-Wafer) packaging technology. The computer you’re using to read this on will have a range of different-sized processors inside it. If your device is a top-tier gaming PC with an RTX 5090, then the GPU will be the biggest single chip it has.
On the other hand, if the CPU is a Ryzen 9 9950X3D or a Core Ultra 9 285K, then your PC will also have lots of tiny chiplets, all packaged together to make one ‘large’ processor. This is essentially what TMSC’s new SoW technology is, albeit on a much grander scale.
Rather than just taking three or four small dies and mounting them on a substrate that’s around 7,000 square millimetres in area, SoW-X (X for eXtreme) covers an area 10 to 15 times larger. It’s so big that an entire 300 mm silicon wafer is required.
TSMC’s first generation of SoW packaging involved mounting just the processing dies to the wafer, whereas the new version will be able to include HBM (High Bandwidth Memory) chips, removing the need to have costly and complex interconnects linking the RAM to the processors.
The whole setup makes the system used to manufacture AMD’s huge MI300X AI processors look decidedly tiny, and those things are hardly what you’d call small. Each one of those comprises 20 chips and chiplets (four big I/O base chiplets, eight CNDA 3 GPUs, and eight HBM modules)—TMSC’s SoW-X could potentially multiply that by a factor of 10.
Naturally, a SoW-X creation isn’t something that you can just drop into a socket. For a start, the wafer on which all the chiplets are mounted has to be layered with structures to remove heat, provide electricity, and transfer data to and from the system. Silicon wafers are slim, delicate things, but once packaged in a SoW-X device, they’re all hulking, heavy, and massive.
These are going to be used for (no prizes for guessing) the very largest AI data centers, where having as much processing power in the smallest amount of space is crucial to maximising the available area within the center’s buildings. SoW-X isn’t just about making bigger and better processors, pushing the limits of Moore’s Law to extreme lengths.
By keeping as many components as possible on the same substrate, power consumption can be greatly reduced. It’s still huge, of course, as TSMC says that SoW-X will be reaching as high as 17,000 W, but it also says the relative performance-per-watt is 65% higher than a traditional data center cluster, where everything is externally connected via PCIe links.
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None of this might seem relevant to gaming PCs and other household devices, but the knowledge and experiences that TSMC gains with shipping SoW-X systems to customers will filter down to its ‘everyday’ packaging technologies.
Phones, desktop CPUs, and graphics cards will all benefit at some point in the future, either because they’re already using chiplets or chip-stacking, or they will once process nodes hit the practical limit to the number of transistors one can stuff into a single die. For now, though, TSMC says we won’t see SoW-X out in the wild until 2027 and even then, the very high cost of doing it all means that only a select few customers will be able to afford it.
A more important question is what’s next after SoW-X? Will the wafers just have to get bigger, or will we see system-on-wafer-on-wafer packaging being developed (I’ve decided that this should be called SoS, system-on-sandwich) to continue the drive to have ever more processing power?
While transistors might not get much smaller, I think we can safely bet that processors are just going to get a lot bigger.
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